包括ifft的配置使用，第三十二期参考资料

20130916, s05e14, when a man is betrayed by a woman, he becomes crazy.

Vivado xilinx fft9.0 使用笔记：

****注仿真实地度量1024点的调换须要通过11四十多个石英钟周期技巧得到更改结果；

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模块配置时域信号含义请参见pg109文书档案手册，不详细表达；

一、查找fft IP核按如下几图配置可达成科学的fft转变结果：

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配置1个转移通道；调换数据长度是1024 points；选取流线型结构类型pipelined,streamingI/O，优点并行转变速度快，,短处占用能源多。如图1：

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图1

如图2，设置数据类型为定位小数；缩减因子设置成Unscaled；RoundingModes设置成Truncation；输入位宽装置贰十六位，精度设置16；Output Ordering 设置成Natural Order；OptionalOutputFieldds勾选XK_INDEX；

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图2

如图3 此页消息主导恒定配置：

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图3

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***注：注意图4中区域有利于帮忙您在编写testbenchs时对s_axis_config_tdata举办配置；

如图4 s_axis_config_tdata
只有1位配置fft的fwd/inv;

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图4

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Testbench代码如下：

`timescale 1ns / 1ps

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//////////////////////////////////////////////////////////////////////////////////

// Company:

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// Engineer: zyp

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// Create Date: 04/21/2017 08:35:42 PM

// Design Name:

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// Module Name: test

// Project Name:

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// Target Devices:

// Tool Versions:

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// Description:

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// Dependencies:

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// Revision:

// Revision 0.01 – File Created

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// Additional Comments:

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//////////////////////////////////////////////////////////////////////////////////

module test();

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// Inputs

reg aclk;

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reg aresetn;//active low

reg s_axis_config_tvalid;

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reg s_axis_data_tvalid;

reg s_axis_data_tlast;

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reg m_axis_data_tready;

reg [7:0] s_axis_config_tdata;

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//reg [15:0] s_axis_config_tdata;

reg [47: 0] s_axis_data_tdata;

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// Outputs

wire s_axis_config_tready;

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wire s_axis_data_tready;

wire m_axis_data_tvalid;

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wire m_axis_data_tlast;

wire event_frame_started;

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wire event_tlast_unexpected;

wire event_tlast_missing;

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wire event_status_channel_halt;

wire event_data_in_channel_halt;

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wire event_data_out_channel_halt;

//wire [47:0] m_axis_data_tdata;

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wire [79:0] m_axis_data_tdata; //un_scaled

wire [15:0] m_axis_data_tuser;

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//reg[23:0] XK_RE;

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//reg[23:0] XK_IM;

reg[39:0] XK_RE;//config unsclaed

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reg[39:0] XK_IM;//config unsclaed

reg[23:0] mem0_re[0:4095];

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reg[23:0] mem1_re[0:7];

reg[23:0] mem2_re[0:7];

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initial $readmemh(“D:/fpga/fft1/stimulus0_24bit.dat”,mem0_re);

initial $readmemh(“D:/fpga/fft1/stimulus1_24bit.dat”,mem1_re);

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initial $readmemh(“D:/fpga/fft1/stimulus2_24bit.dat”,mem2_re);

reg[7:0] op_sample= 0;

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reg op_sample_first = 1;

reg[7:0] ip_frame=0;

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reg[7:0] op_frame=0;

integer i;

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// generate clk

always #5 aclk =! aclk;

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xfft_0 xfft_m0 (

.aclk, // input wire aclk

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// .aresetn,

.s_axis_config_tdata(s_axis_config_tdata), // input wire [7 : 0]
s_axis_config_tdata

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.s_axis_config_tvalid(s_axis_config_tvalid), // input wire
s_axis_config_tvalid

.s_axis_config_tready(s_axis_config_tready), // output wire
s_axis_config_tready

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.s_axis_data_tdata(s_axis_data_tdata), // input wire [47 : 0]
s_axis_data_tdata

.s_axis_data_tvalid(s_axis_data_tvalid), // input wire
s_axis_data_tvalid

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.s_axis_data_tready(s_axis_data_tready), // output wire
s_axis_data_tready

.s_axis_data_tlast(s_axis_data_tlast), // input wire
s_axis_data_tlast

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.m_axis_data_tdata(m_axis_data_tdata), // output wire [47 : 0]
m_axis_data_tdata

.m_axis_data_tvalid(m_axis_data_tvalid), // output wire
m_axis_data_tvalid

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.m_axis_data_tready(m_axis_data_tready), // input wire
m_axis_data_tready

.m_axis_data_tlast(m_axis_data_tlast), // output wire
m_axis_data_tlast

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.m_axis_data_tuser(m_axis_data_tuser),//XK_INDEX

.event_frame_started(event_frame_started), // output wire
event_frame_started

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.event_tlast_unexpected(event_tlast_unexpected), // output wire
event_tlast_unexpected

.event_tlast_missing(event_tlast_missing), // output wire
event_tlast_missing

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.event_status_channel_halt(event_status_channel_halt), // output
wire event_status_channel_halt

.event_data_in_channel_halt(event_data_in_channel_halt), //
output wire event_data_in_channel_halt

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.event_data_out_channel_halt(event_data_out_channel_halt) //
output wire event_data_out_channel_halt

);

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initial begin

// Initialize Inputs

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aclk = 0;

aresetn = 0;

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s_axis_config_tvalid = 0;

s_axis_config_tdata = 0;

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s_axis_data_tvalid = 0;

s_axis_data_tdata = 0;

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s_axis_data_tlast = 0;

m_axis_data_tready = 0;

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// Wait 150 ns for global reset to finish

#150;

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aresetn = 1;

m_axis_data_tready = 1;

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s_axis_config_tvalid = 1;

//s_axis_config_tdata = 16’b10110101011; // 512points bit0-9
sclae_sch bit10 fwd/ivs 这样布置不对
FFT desired (and not
IFFT

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//s_axis_config_tdata = 16’b01101010111; // 512points bit1-10
sclae_sch bit0 fwd/ivs 按那组数据配置结果收缩了一千倍 FFT desired (and not IFFT

//s_axis_config_tdata = 16’b00000000001; // 512points result 与下一种情况同样

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s_axis_config_tdata = 1’b1; // 配置fwd 512 or 1024 points 配置unscale 情状位宽有进位输出位宽要对应
结果正确正确！！！！！

//s_axis_config_tdata = 16’b1101101010111;//4096points bit1-12
sclae_sch bit0 fwd/ivs

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//s_axis_data_tlast = 1;

s_axis_data_tdata = 48’h000000;

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s_axis_data_tvalid = 0;

#10

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s_axis_config_tvalid = 0;

begin

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for(i=0;i<1024;i=i+1) begin

#10

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s_axis_data_tvalid <= 1;

s_axis_data_tdata <= {{24’h000000},mem0_re[i]};

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$display(“mem_a[%d] = %h”, i, mem0_re[i]);

end

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end

assign XK_RE = m_axis_data_tdata[39:0];

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assign XK_IM = m_axis_data_tdata[79:40];

#10;

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s_axis_data_tdata = 48’h000000;

s_axis_data_tvalid = 0;

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#400000 $finish;

end

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endmodule

/*test smaple 1 N=8 (?????s_axis_config_tdata = 8’b00000001);

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s_axis_data_tdata =[1.1 2.1 3.1 4.1 5.1 6.1 7.1 8.1] 16位牢固小数

s_axis_data_tdata =[1199a 2199a 3199a 4199a 5199a 6199a 7199a
8199a] 拾伍个人稳固小数

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vivado_result 00000024ccd0 09a820fc0000 040000fc0000 01a820fc0000
000000fc0000 fe57e0fc0000 fc0000fc0000 f657e0fc0000

matlab_result 36.8000+0.0000i -4.0000+9.6569i -4.0000+4.0000i
-4.0000+1.6569i -4.0000+0.0000i -4.0000-1.6569i -4.0000-4.0000i
-4.0000-9.6569i

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s_axis_config_tdata = 8’b00000000大概不配备

vivado_result 00000024ccd0 f657e0fc0000 fc0000fc0000 fe57e0fc0000
000000fc0000 01a820fc0000 040000fc0000 09a820fc0000

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compare result right!!!!!

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/*test sample 2 N=16 (?????s_axis_config_tdata = 8’b00000001);

s_axis_data_tdata =[1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a
1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a] 16点 16个人稳固小数

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vivado_result 0000004999a0 000000000000 135040f80000 000000000000
080000f80000 000000000000 035040f80000 000000000000 000000f80000
000000000000 fcafc0f80000 000000000000 f80000f80000 000000000000
ecafc0f80000 000000000000

matlab_result 73.6000+0.0000i 0.0000+0.0000i -8.0000+19.3137i
0.0000+0.0000i -8.0000+8.0000i 0.0000+0.0000i -8.0000+3.3137i
0.0000+0.0000i -8.0000+0.0000i 0.0000+0.0000i -8.0000-3.3137i
0.0000+0.0000i -8.0000-8.0000i 0.0000+0.0000i -8.0000-19.3137i
0.0000+0.0000i

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compare result right!!!!!

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/*test sample 3 N=128 (s_axis_config_tdata =
16’b0000000000000001;error )

s_axis_config_tdata = 16’b0101010101010101;error

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s_axis_data_tdata =[1199a 2199a 3199a 4199a 5199a 6199a 7199a
8199a]*8 十五个人牢固小数

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*****注：在那之中输入数据”D:/fpga/fft1/stimulus0_24bit.dat”为16个人牢固小数如下：

1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a
5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a
1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a
5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a
1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a
5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a
1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a
5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a
1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a
5199a 6199a 7199a 8199a 1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a
1199a 2199a 3199a 4199a 5199a 6199a 7199a 8199a

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Vivado simulationresult 如图所示：

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图5

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将上述输入数据调换来16为固定小数为a=[1.1 2.1 3.1 4.1 5.1 6.1 7.1
8.1……..]b=fft MATLAB仿真结果如图：

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图6

相比图5、图6可见结果保持一致。

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二、配置IP核实现ifft转换

Testbench 代码如下：

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`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

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// Engineer: zyp

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// Create Date: 04/21/2017 08:35:42 PM

// Design Name:

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// Module Name: test

// Project Name:

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// Target Devices:

// Tool Versions:

// Description:

// 对512点做ifft变换

// 512样书数量出自【1.1 2.1 3.1 4.1 5.1 6.1 7.1
8.1……】的fft转变结果

// Dependencies:

// Revision:

// Revision 0.01 – File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module testbench_ifft();

//ifft_0信号

// Inputs

reg aclk;

reg aresetn;//active low

reg rst;

reg s_axis_config_tvalid;

reg s_axis_data_tvalid;

reg s_axis_data_tlast;

reg m_axis_data_tready;

reg [7:0] s_axis_config_tdata;

reg [63: 0] s_axis_data_tdata;

// Outputs

wire s_axis_config_tready;

wire s_axis_data_tready;

wire m_axis_data_tvalid;

wire m_axis_data_tlast;

wire event_frame_started;

wire event_tlast_unexpected;

wire event_tlast_missing;

wire event_status_channel_halt;

wire event_data_in_channel_halt;

wire event_data_out_channel_halt;

wire [95:0] m_axis_data_tdata; //un_scaled

wire [15:0] m_axis_data_tuser;

reg[47:0] XK_RE;//ceshi xianshi

reg[47:0] XK_IM;//ceshi xianshi

reg[23:0] mem0_re[0:4095];

reg[63:0] mem3_re[0:511];//高四十一个人是虚部三十八人为有效低43个人是实部三十一个人有效 19个人稳固小数

reg[23:0] mem1_re[0:7];

reg[23:0] mem2_re[0:7];

initial $readmemh(“D:/fpga/fft1/stimulus0_24bit.dat”,mem0_re);

initial $readmemh(“D:/fpga/fft1/stimulus1_24bit.dat”,mem1_re);

initial $readmemh(“D:/fpga/fft1/stimulus2_24bit.dat”,mem2_re);

initial $readmemh(“D:/fpga/fft1/stimulus3_80bit.dat”,mem3_re);

reg[7:0] op_sample= 0;

reg op_sample_first = 1;

reg[7:0] ip_frame=0;

reg[7:0] op_frame=0;

integer i;

reg[11:0] cnt;

// generate clk

always #5 aclk =! aclk;

ifft_0 ifft_m0 (